The first time using a serial AD converter device, the control circuit is controlled using FPGA. Using FPGA for control can achieve high conversion speed, and AD has high efficiency and simpler control during conversion.

CLM2543 is a 12 bit serial A/D converter that uses switch capacitor successive approximation technology to complete the A/D conversion process.,due to its serial input structure, it can save I/O resources of 51 series microcontrollers.

Its characteristics include:

1) 12 bit resolution A/D converter

2) 11 analog input channels

3) 3 built-in self-test modes

4) Built in sampling and holding function

5) Sampling rate of 66ksps

6) 10μs conversion time within the operating temperature range

7) SPI serial interface

8) The maximum linearity error is ± 1LSB

9) Low power supply current (typical value of 1mA)

10) Power down mode current is 4μA

11) On-chip system clock

12) Programmable MSB or LSB preamble

13) End of Conversion (EOC) output

14) With single and bipolar outputs

15) Programmable output data length

1. Pin of CLM2543

A IN0 to A IN10 are analog input terminals;/ CS is the chip selection end; D IN is the serial data input terminal; DOUT is the three-state serial output of the A/D conversion result; EOC is the end of the conversion; CLK is the I/O clock; REF+is the positive reference voltage terminal; REF - is the negative reference voltage terminal; VCC is the power supply; GND is the ground.

1. Usage of CLM2543

2.1 Format of control words

The control word is an 8-bit data input serially from the DATE Input end, which specifies the analog channel to be converted by CLM2543, the length of the converted output data, and the format of the output data. Among them, the high 4 bits (D7-D4) determine the channel number. For channels 0 to 10, this 4 bit is 0000 to 1010H. When it is 1011-1101, it is used for self checking of CLM2543. The values of (Vref+Vref2)/2, Vref+, and Vref2 are tested separately. When it is 1110, CLM2543 enters sleep mode. The low 4 bits determine the length and format of the output data, where D3 and D2 determine the length of the output data, 01 represents the length of the output data as 8 bits, 11 represents the length of the output data as 16 bits, and the rest as 12 bits. D1 determines whether the output data is sent out first in high bits or low bits, and 0 represents the high bits sent out first D0 determines whether the output data is unipolar (binary) or bipolar (complement of 2). If it is unipolar, this bit is 0, otherwise it is 1.

2.2 Conversion process

After powering on, the chip selection/CS must start a work cycle from high to low. At this time, the EOC is high, the input data register is set to 0, and the content of the output data register is random. At the beginning, the chip selection/CS is high, I/O CLOCK and DATA Input are disabled, DATA OUT is in a high resistance state, and EOC is high. Reduce/CS, enable I/O CLOCK and DATA OUT, and disengage DATA OUT from high impedance state. 12 clock signals are sequentially added from the I/O CLOCK end. As the clock signal is added, the control word is fed into CLM2543 bit by bit from DATA OUT at the rising edge of the clock signal (high bit is fed first), while the A/D data converted in the previous cycle, i.e. the data in the output data register, is moved out bit by bit from DATA OUT. After CLM2543 receives the 4th clock signal, the channel number has also been received. At this time, TLC2543 starts sampling the analog signal of the selected channel and maintains it until the falling edge of the 12th clock. At the 12th falling edge of the clock, the EOC decreases and A/D conversion of the sampled analog quantity begins. The conversion time is about 10 μ s. After the conversion is completed, the EOC increases, and the converted data is stored in the output data register for output in the next working cycle. Afterwards, a new work cycle can be initiated.